AXI-Verification architecture, functional coverage and assertions based coverage code
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  1. interface axi_slave_if (input bit clk, resetn);
  2. ///////////////////write address channel
  3. input logic awvalid; /// master is sending new address
  4. output logic awready; /// slave is ready to accept request
  5. input logic [3:0] awid; ////// unique ID for each transaction
  6. input logic [3:0] awlen; ////// burst length AXI3 : 1 to 16, AXI4 : 1 to 256
  7. input logic [2:0] awsize; ////unique transaction size : 1,2,4,8,16 ...128 bytes
  8. input logic [31:0] awaddr; ////write adress of transaction
  9. input logic [1:0] awburst; ////burst type : fixed , INCR , WRAP
  10. /////////////////////write data channel
  11. input logic wvalid; //// master is sending new data
  12. output logic wready; //// slave is ready to accept new data
  13. input logic [3:0] wid; /// unique id for transaction
  14. input logic [31:0] wdata; //// data
  15. input logic [3:0] wstrb; //// lane having valid data
  16. input logic wlast, //// last transfer in write burst
  17. ///////////////write response channel
  18. input logic bready; ///master is ready to accept response
  19. output logic bvalid; //// slave has valid response
  20. output logic [3:0] bid; ////unique id for transaction
  21. output logic [1:0] bresp; /// status of write transaction
  22. ////////////// read address channel
  23. output logic reg arready; //read address ready signal from slave
  24. input logic [3:0] arid; //read address id
  25. input logic [31:0] araddr; //read address signal
  26. input logic [3:0] arlen; //length of the burst
  27. input logic [2:0] arsize; //number of bytes in a transfer
  28. input logic [1:0] arburst;//burst type - fixed, incremental, wrapping
  29. input logic arvalid; //address read valid signal
  30. ///////////////////read data channel
  31. output logic [3:0] rid; //read data id
  32. output logic [31:0]rdata; //read data from slave
  33. output logic [1:0] rresp; //read response signal
  34. output logic rlast; //read data last signal
  35. output logic rvalid; //read data valid signal
  36. input logic rready
  37. //========================== ASSERTIONS========================
  38. // WRITE ADDRESS CHANNEL************************************************************************************************************
  39. //1st.(When awvalid is asserted then it remains asserted until awready is HIGH)
  40. property AXI_AWVALID_AWREADY;
  41. @(posedge clk) awvalid |-> (awvalid throughout (awready[->1]));
  42. endproperty
  43. A1:assert property (AXI_AWVALID_AWREADY);
  44. else `uvm_error("ASSERTION","Failure AXI_AWVALID_AWREADY");
  45. //2nd.(BURST can not cross a 4KB Boundary)
  46. property w_burst_boundary;
  47. @(posedge clk) (awvalid && awready) |-> (((2**awsize)*(awlen+1)) < 4096) ;
  48. endproperty
  49. A2:assert property (w_burst_boundary)
  50. else `uvm_error("ASSERTION","Failure w_burst_boundary");
  51. //3rd.(all write address channel remains stable after AWVALID is asserted)
  52. property AXI_AWVALID_STABLE;
  53. @(posedge clk) $rose(awvalid)|->($stable(awid)&& $stable(awaddr)
  54. &&$stable(awlen)&& $stable(awsize)
  55. &&$stable(awburst))throughout awready[->1];
  56. endproperty
  57. A3:assert property (AXI_AWVALID_STABLE)
  58. else `uvm_error("ASSERTION","Failure AXI_AWVALID_STABLE");
  59. //4th.(AWLEN value is 1,3,7,15 for Wrapping type Burst)
  60. property AWLEN_WRAP_BURST;
  61. @(posedge clk) disable iff(!resetn) (awburst==2'b10) |->(awlen==1|awlen==3||awlen==7||awlen==15);
  62. endproperty
  63. A4:assert property (AWLEN_WRAP_BURST)
  64. else `uvm_error("ASSERTION","Failure AWLEN_WRAP_BURST");
  65. //5th.(AWBURST val cant be 2'b11)
  66. property AWBURST_CANT_2b11;
  67. @(posedge clk) (awvalid && awready) |-> (awburst != 2'b11);
  68. endproperty
  69. A5:assert property (AWBURST_CANT_2b11)
  70. else `uvm_error("ASSERTION","Failure AWBURST_CANT_2b11");
  71. //WRITE DATA CHANNEL**************************************************************************************************************
  72. //1st.
  73. property AXI_WVALID_WREADY;
  74. @(posedge clk) wvalid |-> (wvalid throughout (wready[->1])) ;
  75. endproperty
  76. A6: assert property (AXI_WVALID_WREADY)
  77. else `uvm_error("ASSERTION","Failure AXI_WVALID_WREADY");
  78. //2nd. Property to check whether all write address channel remains stable after WVALID is asserted
  79. property AXI_WVALID_WREADY;
  80. @(posedge clk) $rose(wvalid) |-> ( $stable(wid)
  81. && $stable(wdata)
  82. && $stable(wstrb)
  83. && $stable(wlast)) throughout wready[->1];
  84. endproperty
  85. A7:assert property (AXI_WVALID_STABLE)
  86. else `uvm_error("ASSERTION","Failure AXI_WVALID_STABLE");
  87. //WRITE RESPONSE CHANNEL****************************************************************************************************************
  88. //1st.
  89. property AXI_BVALID_BREADY;
  90. @(posedge clk) bvalid|-> (bvalid throughout (bready[->1])) ;
  91. endproperty
  92. A8:assert property (AXI_BVALID_BREADY)
  93. else `uvm_error("ASSERTION","Failure AXI_BVALID_BREADY");
  94. //2nd.to check whether all write address channel remains stable after BVALID is asserted
  95. property AXI_BVALID_STABLE;
  96. @(posedge clk) $rose(bvalid)|->($stable(bid)&& $stable(bresp))throughout bready[->1];
  97. endproperty
  98. A9:assert property (AXI_BVALID_STABLE)
  99. else `uvm_error("ASSERTION","Failure AXI_BVALID_STABLE");
  100. //READ ADDRESS CHANNEL***********************************************************************************************
  101. //1st.
  102. property AXI_ARVALID_ARREADY;
  103. @(posedge clk) arvalid |-> (arvalid throughout (arready[->1])) ;
  104. endproperty
  105. B1:assert property AXI_ARVALID_ARREADY;
  106. else`uvm_error("ASSERTION","Failure AXI_ARVALID_ARREADY");
  107. //2nd.(BURST can not cross a 4KB Boundary)
  108. property r_burst_boubadary;
  109. @(posedge clk) (arvalid && arready) |-> (((2**arsize)*(arlen+1)) < 4096);
  110. endproperty
  111. B2:assert property (r_burst_boubadary)
  112. else `uvm_error("ASSERTION","Failure r_burst_boubadary");
  113. //3rd.(ARLEN value is 1,3,7,15 for Wrapping type Burst)
  114. property ARLEN_WRAP_BURST;
  115. @(posedge clk) disable iff (!resetn) (arburst==2'b10) |-> (arlen==1 || arlen==3 || arlen==7 || arlen==15);
  116. endproperty
  117. B3:assert property (ARLEN_WRAP_BURST)
  118. else `uvm_error("ASSERTION","Failure ARLEN_WRAP_BURST");
  119. //4th.(arburst val cant be 2'b11)
  120. property ARBURST_CANT_2b11; //
  121. @(posedge clk) (arvalid && arready) |-> (arburst != 2'b11);
  122. endproperty
  123. B4:assert property (ARBURST_CANT_2b11)
  124. else `uvm_error("ASSERTION","Failure ARBURST_CANT_2b11");
  125. //5th. Property to check whether all write address channel remains stable after ARVALID is asserted
  126. property AXI_ARVALID_STABLE;
  127. @(posedge clk) $rose(arvalid) |-> ( $stable(arid)
  128. &&$stable(araddr)
  129. &&$stable(arlen)
  130. &&$stable(arsize)
  131. &&$stable(arburst)) throughout arready[->1];
  132. endproperty
  133. B5:assert property (AXI_ARVALID_STABLE)
  134. else `uvm_error("ASSERTION","Failure AXI_ARVALID_STABLE");
  135. //READ DATA CHANNEL***********************************************************************************************************
  136. /1st.
  137. property AXI_RVALID_RREADY;
  138. @(posedge clk) rvalid |-> (rvalid throughout (rready[->1]));
  139. endproperty
  140. B6:assert property (AXI_RVALID_RREADY)
  141. else `uvm_error("ASSERTION","Failure AXI_RVALID_RREADY");
  142. //2nd.to check whether all write address channel remains stable after RVALID is asserted
  143. property AXI_RVALID_STABLE;
  144. @(posedge clk) $rose(rvalid) |-> ( $stable(rid)
  145. && $stable(rdata)
  146. && $stable(rresp)
  147. && $stable(rlast)) throughout rready[->1];
  148. endproperty
  149. B7:assert property (AXI_RVALID_STABLE)
  150. else`uvm_error("ASSERTION","Failure AXI_RVALID_STABLE");
  151. endinterface