AXI-Verification architecture, functional coverage and assertions based coverage code
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  1. `include "uvm_macros.svh"
  2. import uvm_pkg::*;
  3. class axi_txn extends uvm_sequence_item ;
  4. function new(string name = "axi_txn");
  5. super.new(name);
  6. endfunction
  7. ///////////////////write address channel
  8. logic awvalid;// master is sending new address
  9. logic awready; /// slave is ready to accept request
  10. randc bit [3:0] awid; ////// unique ID for each transaction
  11. randc logic [3:0] awlen; ////// burst length AXI3 : 1 to 16, AXI4 : 1 to 256
  12. rand logic [2:0] awsize; ////unique transaction size : 1,2,4,8,16 ...128 bytes
  13. rand logic [31:0] awaddr; ////write adress of transaction
  14. randc logic [1:0] awburst; ////burst type : fixed , INCR , WRAP
  15. /////////////////////write data channel
  16. logic wvalid; //// master is sending new data
  17. logic wready; //// slave is ready to accept new data
  18. randc bit [3:0] wid;/// unique id for transaction
  19. rand logic [31:0] wdata; //// data
  20. rand logic [3:0] wstrb; //// lane having valid data
  21. logic wlast; //// last transfer in write burst
  22. ///////////////write response channel
  23. logic bready; ///master is ready to accept response
  24. logic bvalid; //slave has valid response
  25. bit [3:0] bid; ////unique id for transaction
  26. logic [1:0] bresp; /// status of write transaction
  27. ////////////// read address channel
  28. logic arready; //read address ready signal from slave
  29. logic arvalid; //address read valid signal
  30. randc bit [3:0] arid; //read address id
  31. rand logic [31:0] araddr; //read address signal
  32. randc logic [3:0] arlen; //length of the burst
  33. randc logic [2:0] arsize; //number of bytes in a transfer
  34. logic [1:0] arburst;//burst type - fixed, incremental, wrapping
  35. ///////////////////read data channelogic [3:0] rid; //read data id
  36. logic [31:0]rdata; //read data from slave
  37. logic [1:0] rresp; //read response signal
  38. logic rlast; //read data last signal
  39. logic rvalid; //read data valid signal
  40. logic rready;
  41. bit rid;
  42. `uvm_object_param_utils_begin(axi_txn)
  43. `uvm_field_int(awready,UVM_ALL_ON)
  44. `uvm_field_int(awvalid,UVM_ALL_ON)
  45. `uvm_field_int(awburst,UVM_ALL_ON)
  46. `uvm_field_int(awsize,UVM_ALL_ON)
  47. `uvm_field_int(awlen,UVM_ALL_ON)
  48. `uvm_field_int(awaddr,UVM_ALL_ON)
  49. `uvm_field_int(awid,UVM_ALL_ON)
  50. `uvm_field_int(wready,UVM_ALL_ON)
  51. `uvm_field_int(wvalid,UVM_ALL_ON)
  52. `uvm_field_int(wlast,UVM_ALL_ON)
  53. `uvm_field_int(wstrb,UVM_ALL_ON)
  54. `uvm_field_int(wdata,UVM_ALL_ON)
  55. `uvm_field_int(wid,UVM_ALL_ON)
  56. `uvm_field_int(bid,UVM_ALL_ON)
  57. `uvm_field_int(bresp,UVM_ALL_ON)
  58. `uvm_field_int(bvalid,UVM_ALL_ON)
  59. `uvm_field_int(bready,UVM_ALL_ON)
  60. `uvm_field_int(arready,UVM_ALL_ON)
  61. `uvm_field_int(arvalid,UVM_ALL_ON)
  62. `uvm_field_int(arburst,UVM_ALL_ON)
  63. `uvm_field_int(arsize,UVM_ALL_ON)
  64. `uvm_field_int(arlen,UVM_ALL_ON)
  65. `uvm_field_int(araddr,UVM_ALL_ON)
  66. `uvm_field_int(arid,UVM_ALL_ON)
  67. `uvm_field_int(rready,UVM_ALL_ON)
  68. `uvm_field_int(rvalid,UVM_ALL_ON)
  69. `uvm_field_int(rlast,UVM_ALL_ON)
  70. `uvm_field_int(rresp,UVM_ALL_ON)
  71. `uvm_field_int(rdata,UVM_ALL_ON)
  72. `uvm_field_int(rid,UVM_ALL_ON)
  73. `uvm_object_utils_end
  74. //--------------------
  75. // Same ID constraint for write transactions
  76. constraint same_wr_id { awid==wid;}
  77. // Same ID constraint for read transactions
  78. constraint same_rd_id { arid==rid;}
  79. //-----------------------------------------------------------------------------
  80. //--------------
  81. //4KB address boundary for write address channel
  82. constraint awdder_4kb {awadder %4096 + (awlen+1 << awsize) <= 4096;}
  83. //4KB address boundary for read address channel
  84. constraint ardder_4kb {aradder % 4096 + (arlen+1 << arsize) <= 4096;}
  85. //---------------------------------------------------------------------------------
  86. //--------------------
  87. //support 1 to 16 awlen. so max write data size is 16*(2**awsize)
  88. //awburst!=2'b10(means-> if it's not wrap type)
  89. constraint wr_data_size {if (awburst !=2'b10)
  90. wdata inside {[1:(16*(2**awsize))]}; }
  91. //support 1 to 16 arlen. so max write data size is 16*(2**arsize)
  92. //arburst!=2'b10(means-> if it's not wrap type)
  93. constraint rd_data_size {if (arburst !=2'b10)
  94. rdata inside {[1:(16*(2**arsize))]}; }
  95. //----------------------------------------------------------------------------
  96. //-------------------
  97. // bcs for Wrapping burst the length of the burst must be 2, 4, 8, or 16.
  98. //so therefore write data should be multiple of BL(2,4,8, or 16) and (2**awsize)
  99. constraint awburst_val {if (awburst ==2'b10)
  100. {wdata inside {((2**awsize)*2),((2**awsize)*4),((2**awsize)*8),((2**awsize)*16)}; }}
  101. // bcs for Wrapping burst the length of the burst must be 2, 4, 8, or 16.
  102. //so therefore write data should be multiple of BL(2,4,8, or 16) and (2**arsize)
  103. constraint arburst_val {if (arburst ==2'b10)
  104. {rdata inside {((2**arsize)*2),((2**arsize)*4),((2**arsize)*8),((2**arsize)*16)}; }}
  105. //------------------------------------------------------------------------------
  106. //--------------------
  107. //for Wrapping burst the length of the burst must be 2, 4, 8, or 16 (bcs BL= axlen+1)
  108. constraint awburst_val {if (awburst==2'b10) {awlen inside {1,3,7,15};}}
  109. //for Wrapping burst the length of the burst must be 2, 4, 8, or 16 (bcs BL= axlen+1)
  110. constraint arburst_val {if (arburst==2'b10) {arlen inside {1,3,7,15};}}
  111. //---------------------------------------------------------------------------------
  112. endclass: axi_txn
  113. module top;
  114. axi_txn txt;
  115. initial begin
  116. repeat(10) begin
  117. txt=new();
  118. txt.randomize();
  119. $display("pass");
  120. end end
  121. endmodule