class axi_slave_p_mon extends uvm_monitor;
`uvm_component_utils(axi_slave_p_mon)
uvm_analysis_port #(axi_txn) ap;
virtual axi_slave_if vif;
axi_txn mon_txn;
function new( string name = "axi_slave_p_mon", uvm_component parent = null);
super.new(name, parent);
ap = new("ap",this);
mon_txn= new ("mon_txn");
endfunction

virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
  if (!uvm_config_db#(virtual axi_slave_if)::get(this,"","vif",vif))
   begin
		`uvm_error( get_type_name(),"Not able to get AXI INTF HANDLE")
   end
 endfunction



 virtual task run_phase(uvm_phase phase);
	forever begin
		@(vif);
		//WA
		if (vif.awvalid == 1 && vif.awready == 1)begin
			mon_txn = axi_tx::type_id::create("mon_txn");
			mon_txn.awre = vif.awaddr;
			mon_txn.awlen = vif.awlen;
			mon_txn.awsize = vif.awsize;
			mon_txn.awburst = burst_type_t'(vif.mon_cb.awburst);
			tx.tx_id = vif.mon_cb.awid;
			num_writes = 0;
		end
		//WD
		if (vif.mon_cb.wvalid == 1 && vif.mon_cb.wready == 1)begin
		num_writes++;
			if (num_writes > 1)begin
				tx.dataQ.push_back(vif.mon_cb.wdata);
			end
		end
		//WR(B)
		if (vif.mon_cb.bvalid == 1 && vif.mon_cb.bready == 1)begin
			tx.resp = vif.mon_cb.bresp;
			ap_port.write(tx);
		end
		//RA
		if (vif.mon_cb.arvalid == 1 && vif.mon_cb.arready == 1)begin
			tx = axi_tx::type_id::create("tx");
			tx.wr_rd = 1'b0;
			tx.addr = vif.mon_cb.araddr;
			tx.burst_len = vif.mon_cb.arlen;
			tx.burst_size = vif.mon_cb.arsize;
			tx.burst_type = burst_type_t'(vif.mon_cb.arburst);
			tx.tx_id = vif.mon_cb.arid;
			num_reads = 0;
		end
		//RD
		if (vif.mon_cb.rvalid == 1 && vif.mon_cb.rready == 1)begin
		num_reads++;
			if(num_reads > 1)begin
				tx.dataQ.push_back(vif.mon_cb.rdata);
			end
			if (vif.mon_cb.rlast == 1)begin
				ap_port.write(tx);
			end
		end
	end
endtask
endclass