`include "uvm_macros.svh"
 import uvm_pkg::*;
 import my_pkg::*;
`include "design.sv"
`include "pkg.sv"
`include "axi_sequence_item.sv"
`include "axi_sequence.sv"
`include "axi_sequencer.sv"
`include "axi_env.sv"
`include "axi_interface.sv"
`include "axi_driver.sv"
`include "axi_test.sv"
`include "axi_agent.sv"
module top; 
 //interface instance
  axi_if vif ();
  
  //connecting dut signals with interface and gloable signals
  axi_slave dut(.clk(vif.clk),
              .resetn(vif.resetn),
              ///////////////////write address channel
              .awvalid(vif.awvalid),
              .awready(vif.awready),
              .awid(vif.awid),
              .awlen(vif.awlen),
              .awsize(vif.awsize),
              .awaddr(vif.awaddr),
              .awburst(vif.awburst),
           /////////////////////write data channel  
             .wvalid(vif.wvalid),
              .wready(vif.wready),
              .wid(vif.wid),
              .wdata(vif.wdata),
              .wstrb(vif.wstrb),
              .wlast(vif.wlast),   
            ///////////////write response channel
              .bready(vif.bready),
              .bvalid(vif.bvalid),
              .bid(vif.bid),
              .bresp(vif.bresp),               
            ////////////// read address channel
              .arready(vif.arready),
              .arid(vif.arid),
              .araddr(vif.araddr),
              .arlen(vif.arlen),
              .arsize(vif.arsize),
              .arburst(vif.arburst),
              .arvalid(vif.arvalid),  
           ///////////////////read data channel
             .rid(vif.rid),
              .rdata(vif.rdata),
              .rresp(vif.rresp),
              .rlast(vif.rlast),
              .rvalid(vif.rvalid),
              .rready(vif.rready));
  
  initial begin
    vif.clk <= 0;
    vif.resetn <=0; 
  end
  
  initial begin
    #10
    vif.resetn <=1; 
  end
 
  //clock generator
  always #5 vif.clk <= ~vif.clk;
  
  initial begin
    //pass interface to lower hierarchy
    uvm_config_db#(virtual axi_if)::set(null, "*", "vif", vif);
    run_test("give test name please");// need to write UVM_test name 
 end

 initial begin
  $dumpfile("dump.vcd");
   $dumpvars;
 end 
endmodule