class axi_coverage extends uvm_subscriber#(sequence_item);
`uvm_component_utils(axi_coverage)
sequence_item txn;
// Coverpoints for low power interface signals
covergroup t1;
 coverpoint CSYSACK; 
coverpoint CSYSREQ;
 coverpoint CACTIVE;
 // Cross coverage between low power interface signals
 cross low_power_cross = {CSYSACK, CSYSREQ, CACTIVE};
endgroup
//t2
covergroup t2;
coverpoint awid{ bins ids[] =[1:16]};}
coverpoint awlen{ bins len _values[] ={[1:16]};}
cp1: coverpoint awsize 
cp2: coverpoint awaddr { 2^0 to 2^31;}
cp3:coverpoint awburst{  bins busttype[] = [0:3];}
endgroup

//t3
covergroup t3;
coverpoint awlen { bins len_values[] = {[0:16], [17:32], [33:48], [49:64]}; } 
coverpoint wlast;
 // Coverpoints for read data coverpoint arlen { bins len_values[] = {[0:15]}; }
 coverpoint rlast; // Cross coverage between write and read data 
cross w_r_data_cross = {awlen, arlen, wlast, rlast};
endgroup

//t4
covergroup t4;
coverpoint awid{ bins ids[] =[1:16]};}
coverpoint awlen{ bins len _values[] ={[1:16]};}
cp1: coverpoint awsize 
cp2: coverpoint awaddr { 2^0 to 2^31;}
cp3:coverpoint awburst{  bins busttype[] = [0:3];}
// Coverpoints for address signals 
coverpoint awaddr { bins addr_range[] = {[0:255], [256:511], [512:767], [768:1023]};
 bins addr_alignment[] = {[0], [4], [8], [12], [16], [20], [24], [28], [32]}; } 
coverpoint araddr { bins addr_range[] = {[0:255], [256:511], [512:767], [768:1023]}; 
bins addr_alignment[] = {[0], [4], [8], [12], [16], [20], [24], [28], [32]}; }
 // Cross coverage between awaddr and araddr
 cross aw_ar_address_cross = {awaddr, araddr};
endgroup

//t5
covergroup t5;
// Coverpoints for read address
 coverpoint araddr { bins addr_range[] = {[0:255], [256:511], [512:767], [768:1023]}; 
bins addr_alignment[] = {[0], [4], [8], [12], [16], [20], [24], [28], [32]}; } 
// Cross coverage between read address and burst length
 cross araddr_arlen_cross = {araddr, arlen};
endgroup

//t6
covergroup t6;
// Coverpoints for read data
 coverpoint rdata { bins data_values[] = {[0:255], [256:511], [512:767], [768:1023]}; } 
coverpoint rvalid;
 // Cross coverage between read data and response 
cross rdata_rresp_cross = {rdata, rresp};
 cross rdata_rvalid_cross = {rdata, rvalid};
endgroup

//t7
covergroup t7;
// Coverpoints for low power interface signals
 coverpoint CSYSACK; 
coverpoint CSYSREQ;
 coverpoint CACTIVE;
 // Cross coverage between low power interface signals
 cross low_power_cross = {CSYSACK, CSYSREQ, CACTIVE};
endgroup

//t8
covergroup t8;
// Coverpoints for address signals 
coverpoint awaddr { bins addr_range[] = {[0:255], [256:511], [512:767], [768:1023]};
 bins addr_alignment[] = {[0], [4], [8], [12], [16], [20], [24], [28], [32]}; } 
coverpoint araddr { bins addr_range[] = {[0:255], [256:511], [512:767], [768:1023]}; 
bins addr_alignment[] = {[0], [4], [8], [12], [16], [20], [24], [28], [32]}; }
 // Cross coverage between awaddr and araddr
 cross aw_ar_address_cross = {awaddr, araddr};
// Coverpoints for write response 
coverpoint bresp { bins resp_values[] = {[0:1], [2]}; } 
// Coverpoints for read response 
coverpoint rresp { bins resp_values[] = {[0:1], [2]}; } 
// Cross coverage between write and read responses
 cross b_r_resp_cross = {bresp, rresp};

endgroup


 
 


function new(string name, uvm_component parent);
t1=new();
t2=new();
t3=new();
t4=new();
t5=new();
t8=new();
endfunction
endclass