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axi_formal_driver1.sv
Целия файл
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| //driver | |||
| class driver extends uvm_driver #(packet); | |||
| `uvm_component_utils(driver) | |||
| virtual axi_if vif; | |||
| packet pkt; | |||
| function new(string name="driver", uvm_component parent=null); | |||
| super.new(name, parent); | |||
| endfunction | |||
| virtual function void build_phase(uvm_phase phase); | |||
| super.build_phase(phase); | |||
| pkt=packet::type_id::create("pkt"); | |||
| if(!uvm_config_db#(virtual axi_if)::get(this,"","vif",vif)) | |||
| `uvm_error("drv","Unable to access Interface"); | |||
| endfunction | |||
| task reset_dut(); | |||
| repeat (2) begin | |||
| //write address channel | |||
| vif.awvalid <= 0; | |||
| vif.awready <= 0; | |||
| vif.awid <= 0; | |||
| vif.awlen <= 0; | |||
| vif.awsize <= 0; | |||
| vif.awaddr <= 0; | |||
| vif.awburst <= 0; | |||
| //write data channel (w) | |||
| vif.wvalid <= 0; | |||
| vif.wready <= 0; | |||
| vif.wid <= 0; | |||
| vif.wdata <= 0; | |||
| vif.wstrb <= 0; | |||
| vif.wlast <= 0; | |||
| //write response channel (b) | |||
| vif.bready <= 0; | |||
| vif.bvalid <= 0; | |||
| vif.bid <= 0; | |||
| vif.bresp <= 0; | |||
| ///////////////read address channel (ar) | |||
| vif.arvalid <= 0; | |||
| vif.arready <= 0; | |||
| vif.arid <= 0; | |||
| vif.arlen <= 0; | |||
| vif.arsize <= 0; | |||
| vif.araddr <= 0; | |||
| vif.arburst <= 0; | |||
| /////////// read data channel (r) | |||
| vif.rvalid <= 0; | |||
| vif.rready <= 0; | |||
| vif.rid <= 0; | |||
| vif.rdata <= 0; | |||
| vif.rstrb <= 0; | |||
| vif.rlast <= 0; | |||
| vif.rresp <= 0; | |||
| //1 clk delay | |||
| @(posedge vif.clk); | |||
| `uvm_info(get_type_name(),"*** Reset Applied by driver ***",UVM_MEDIUM) | |||
| end | |||
| endtask | |||
| task write(); | |||
| if(pkt.op==WRITE) | |||
| begin | |||
| //write address channel | |||
| vif.awvalid <= pkt.awvalid ; | |||
| vif.awready <= pkt.awready ; | |||
| vif.awid <= pkt.awid ; | |||
| vif.awlen <= pkt.awlen ; | |||
| vif.awsize <= pkt.awsize ; | |||
| vif.awaddr <= pkt.awaddr ; | |||
| vif.awburst <= pkt.awburst ; | |||
| //write data channel (w) | |||
| vif.wvalid <= pkt.wvalid ; | |||
| vif.wready <= pkt.wready ; | |||
| vif.wid <= pkt.wid ; | |||
| vif.wdata <= pkt.wdata ; | |||
| vif.wstrb <= pkt.wstrb ; | |||
| vif.wlast <= pkt.wlast ; | |||
| //write response channel (b) | |||
| vif.bready <= pkt.bready ; | |||
| vif.bvalid <= pkt.bvalid ; | |||
| vif.bid <= pkt.bid ; | |||
| //1 clk delay | |||
| @(posedge vif.clk); | |||
| `uvm_info(get_type_name(),"*** write signals are drived to DUT ***",UVM_MEDIUM) | |||
| vif.bresp <= pkt.bresp ; end | |||
| endtask | |||
| task read(); | |||
| if(pkt.op == READ)begin | |||
| ///////////////read address channar) | |||
| vif.arvalid <= pkt.arvalid ; | |||
| vif.arready <= pkt.arready ; | |||
| vif.arid <= pkt.arid ; | |||
| vif.arlen <= pkt.arlen ; | |||
| vif.arsize <= pkt.arsize ; | |||
| vif.araddr <= pkt.araddr ; | |||
| vif.arburst <= pkt.arburst ; | |||
| /////////// read data channel (r) | |||
| vif.rvalid <= pkt.rvalid ; | |||
| vif.rready <= pkt.rready ; | |||
| vif.rid <= pkt.rid ; | |||
| vif.rdata <= pkt.rdata ; | |||
| vif.rstrb <= pkt.rstrb ; | |||
| vif.rlast <= pkt.rlast ; | |||
| vif.rresp <= pkt.rresp ; | |||
| //1 clk delay | |||
| @(posedge vif.clk); | |||
| `uvm_info(get_type_name(),"*** read signals are drived to DUT ***",UVM_MEDIUM) | |||
| end | |||
| endtask | |||
| virtual task run_phase(uvm_phase phase); | |||
| reset_dut(); | |||
| forever begin | |||
| seq_item_port.get_next_item(pkt); | |||
| `uvm_info(get_type_name(),"*** Driver Received the transaction by sequencer ***",UVM_MEDIUM) | |||
| if(pkt.op==RESET) begin | |||
| reset_dut(); | |||
| end | |||
| //Write operation support | |||
| else if(pkt.op == WRITE) begin | |||
| write(); | |||
| `uvm_info(get_type_name(),"*** WRITE packet is received in driver ***",UVM_MEDIUM) | |||
| end | |||
| else if(pkt.op == READ) begin | |||
| read(); | |||
| `uvm_info(get_type_name(),"*** READ packet is received in driver ***",UVM_MEDIUM) | |||
| end | |||
| //put read drive logic here | |||
| seq_item_port.item_done(); | |||
| end | |||
| endtask | |||
| endclass | |||