AXI-Verification/axi_txn1.sv

`include "uvm_macros.svh"
 import uvm_pkg::*;
class axi_txn extends uvm_sequence_item  ;

function new(string name = "axi_txn");
    super.new(name);
  endfunction

///////////////////write address channel
 logic  awvalid;// master is sending new address 
 logic  awready; /// slave is ready to accept request
 randc  bit [3:0] awid; ////// unique ID for each transaction
 randc  logic [3:0] awlen; ////// burst length AXI3 : 1 to 16, AXI4 : 1 to 256
 rand  logic [2:0] awsize; ////unique transaction size : 1,2,4,8,16 ...128 bytes
 rand  logic [31:0] awaddr; ////write adress of transaction
 randc  logic [1:0] awburst; ////burst type : fixed , INCR , WRAP
 

 /////////////////////write data channel
logic wvalid; //// master is sending new data
logic wready; //// slave is ready to accept new data 
randc  bit [3:0] wid;/// unique id for transaction
rand  logic  [31:0] wdata; //// data 
rand  logic  [3:0] wstrb; //// lane having valid data
logic wlast; //// last transfer in write burst


 ///////////////write response channel
logic bready; ///master is ready to accept response
logic bvalid; //slave has valid response
bit [3:0] bid; ////unique id for transaction
logic [1:0] bresp; /// status of write transaction


 ////////////// read address channel
 logic arready; //read address ready signal from slave
 logic arvalid; //address read valid signal
 randc bit [3:0] arid; //read address id
 rand  logic [31:0] araddr; //read address signal
 randc logic [3:0] arlen; //length of the burst
 randc logic [2:0] arsize; //number of bytes in a transfer
 logic [1:0] arburst;//burst type - fixed, incremental, wrapping
 

///////////////////read data channelogic [3:0] rid; //read data id
logic [31:0]rdata; //read data from slave
logic [1:0] rresp; //read response signal
logic rlast; //read data last signal
logic rvalid; //read data valid signal
logic rready;
bit rid;

`uvm_object_param_utils_begin(axi_txn)

    `uvm_field_int(awready,UVM_ALL_ON)
    `uvm_field_int(awvalid,UVM_ALL_ON)
    `uvm_field_int(awburst,UVM_ALL_ON)
    `uvm_field_int(awsize,UVM_ALL_ON)
    `uvm_field_int(awlen,UVM_ALL_ON)
    `uvm_field_int(awaddr,UVM_ALL_ON)
    `uvm_field_int(awid,UVM_ALL_ON)

    `uvm_field_int(wready,UVM_ALL_ON)
    `uvm_field_int(wvalid,UVM_ALL_ON)
    `uvm_field_int(wlast,UVM_ALL_ON)
    `uvm_field_int(wstrb,UVM_ALL_ON)
    `uvm_field_int(wdata,UVM_ALL_ON)
    `uvm_field_int(wid,UVM_ALL_ON)
    
    `uvm_field_int(bid,UVM_ALL_ON)
    `uvm_field_int(bresp,UVM_ALL_ON)
    `uvm_field_int(bvalid,UVM_ALL_ON)
    `uvm_field_int(bready,UVM_ALL_ON)

    `uvm_field_int(arready,UVM_ALL_ON)
    `uvm_field_int(arvalid,UVM_ALL_ON)
    `uvm_field_int(arburst,UVM_ALL_ON)
    `uvm_field_int(arsize,UVM_ALL_ON)
    `uvm_field_int(arlen,UVM_ALL_ON)
    `uvm_field_int(araddr,UVM_ALL_ON)
    `uvm_field_int(arid,UVM_ALL_ON)

    `uvm_field_int(rready,UVM_ALL_ON)
    `uvm_field_int(rvalid,UVM_ALL_ON)
    `uvm_field_int(rlast,UVM_ALL_ON)
    `uvm_field_int(rresp,UVM_ALL_ON)
    `uvm_field_int(rdata,UVM_ALL_ON)
    `uvm_field_int(rid,UVM_ALL_ON)
  `uvm_object_utils_end 

  
//--------------------
// Same ID constraint for write transactions
constraint same_wr_id { awid==wid;}


// Same ID constraint for read transactions
constraint same_rd_id { arid==rid;}
//-----------------------------------------------------------------------------




//--------------
//4KB address boundary for write address channel
constraint awdder_4kb {awadder %4096 + (awlen+1 << awsize) <= 4096;}

//4KB address boundary for read address channel
constraint ardder_4kb {aradder % 4096 + (arlen+1 << arsize) <= 4096;}

//---------------------------------------------------------------------------------




//--------------------
//support 1 to 16 awlen. so max write data size is 16*(2**awsize)
//awburst!=2'b10(means-> if it's not wrap type)
constraint wr_data_size {if (awburst !=2'b10)
                             wdata inside {[1:(16*(2**awsize))]}; }


//support 1 to 16 arlen. so max write data size is 16*(2**arsize)
//arburst!=2'b10(means-> if it's not wrap type)
constraint rd_data_size {if (arburst !=2'b10)
                             rdata inside {[1:(16*(2**arsize))]}; }
//----------------------------------------------------------------------------





//-------------------
// bcs for Wrapping burst the length of the burst must be 2, 4, 8, or 16.                   
//so therefore write data should be multiple of BL(2,4,8, or 16) and (2**awsize)
constraint awburst_val {if (awburst ==2'b10)
        {wdata inside {((2**awsize)*2),((2**awsize)*4),((2**awsize)*8),((2**awsize)*16)}; }}


// bcs for Wrapping burst the length of the burst must be 2, 4, 8, or 16.                   
//so therefore write data should be multiple of BL(2,4,8, or 16) and (2**arsize)
constraint arburst_val {if (arburst ==2'b10)
        {rdata inside {((2**arsize)*2),((2**arsize)*4),((2**arsize)*8),((2**arsize)*16)}; }}
//------------------------------------------------------------------------------





//--------------------
//for Wrapping burst the length of the burst must be 2, 4, 8, or 16 (bcs BL= axlen+1)
constraint awburst_val {if (awburst==2'b10) {awlen inside {1,3,7,15};}}


//for Wrapping burst the length of the burst must be 2, 4, 8, or 16 (bcs BL= axlen+1)
constraint arburst_val {if (arburst==2'b10) {arlen inside {1,3,7,15};}}
//---------------------------------------------------------------------------------

endclass: axi_txn


module top;
axi_txn txt;
initial begin
	repeat(10) begin
	txt=new();
	txt.randomize();
	$display("pass");
end end
endmodule