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charan_axi_code/axi_driver.sv

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  1. class driver extends uvm_driver #(seq);

  2.  `uvm_component_utils(driver)

  3. 

  4. virtual axi_driver_if vif;

  5. sequence seq;

  6.   

  7.   function new(string name="driver", uvm_component parent=null);

  8.  super.new(name, parent);

  9.  endfunction

  10. 

  11.   virtual function void build_phase(uvm_phase phase);

  12.     super.build_phase(phase);

  13.     seq=sequence::type_id::create("seq");

  14.     if(!uvm_config_db#(virtual axi_driver_if)::get(this," ","vif",vif))

  15.       `uvm_error("driver"," Interface not set");

  16.   endfunction

  17.  

  18.   task reset();

  19.     begin

  20.       

  21.   		vif.awvalid     	<= 0;

  22.   		vif.awready		<= 0;

  23.   		vif.awid 		<= 0;

  24.   		vif.awlen 		<= 0;

  25.  		vif.awsize 		<= 0;

  26.  		vif.awaddr 		<= 0;   

  27.                 vif.awburst		<= 0; 

  28.   		vif.wvalid 		<= 0;

  29.   		vif.wready		<= 0;

  30.   		vif.wid 		<= 0;

  31.   		vif.wdata 		<= 0;

  32.  		vif.wstrb 		<= 0;

  33.  		vif.wlast 		<= 0; 

  34.    		vif.bready 		<= 0;

  35.   		vif.bvalid 		<= 0;

  36.  		vif.bid 		<= 0;

  37.  		vif.bresp 		<= 0;        

  38.   		vif.arvalid 	        <= 0;

  39.   		vif.arready		<= 0;

  40.   		vif.arid 		<= 0;

  41.   		vif.arlen 		<= 0;

  42.  		vif.arsize 		<= 0;

  43.  		vif.araddr 		<= 0;   

  44.                vif.arburst		<= 0;      

  45.    		vif.rvalid       	<= 0;

  46. 		vif.rready		<= 0;

  47.   		vif.rid 		<= 0;

  48.   		vif.rdata 		<= 0;

  49.  		vif.rstrb 		<= 0;

  50.  		vif.rlast 		<= 0;   

  51.                vif.rresp		<= 0;         

  52.       @(posedge vif.clk);

  53.       `uvm_info(get_type_name(),"reset applied",UVM_MEDIUM)      

  54.   end

  55.  endtask

  56.   virtual task run_phase(uvm_phase phase);

  57.     reset();   

  58.    seq_tem_port.get_next_item(txn); 

  59.     if(wr_rd==1)

  60.           begin

  61.           wrtie_address();

  62. 	  write_data();

  63. 	  write_response();

  64.           end

  65.   else

  66.           begin

  67. 	  read_address();

  68. 	  read_data();

  69.           end

  70.   endtask

  71.    virtual task write_address();

  72.         vif.awready<=0;

  73.         vif.awaddr<= txn.awaddr;

  74.         vif.awsize<= txn.awsize;

  75.         vif.awlen<= txn.awlen;

  76.         vif.awcache<= txn.awcache;

  77.         vif.awburst<= txn.awburst;

  78.         vif.awvalid<=1'b1;

  79.         case (txn.awburst)

  80. 		2'b00 : write_ad_fixed_burst;

  81. 		2'b01 : write_ad_incr_burst;

  82. 		2'b10 : write_ad_wrap_burst;

  83. 	endcase

  84. 	while(vif.awready==0)

  85. 	$display("within loop");

  86. begin

  87. 	@(posedge vif.clk);

  88. 	if(vif.awvalid==1)

  89. 	begin 

  90. 	awready=1;

  91. 	$display("write address phase is completed");

  92. end

  93. end

  94. vif.awvalid=0;

  95. endtask

  96. 

  97. ////////////////// wridte_fixed burst////////////////

  98.  virtual task write_ad_fixed_burst();

  99.         vif.awlen  <= txn.awlen;

  100.         vif.awid   <= txn.awid;

  101. 	vif.awaddr <= txn.awaddr;

  102. 	vif.awsize<= txn.awsize;

  103. 	vif.awvalid<= 1;

  104.       wait(vif.awready);

  105. 	vif.awvalid<=0;

  106. 	write_data();

  107. endtask

  108.  virtual task write_data();

  109.      vif.wready<=0;

  110.     for(int i=0;i<=txn.awlen+1;i++) begin

  111. 	    $display("write data started");

  112. 	    vif.wdata<=txn.wdata[i];

  113. 	    vif.wstrb<=txn.wstrb[i];

  114. 	    vif.wid<=txn.wid;

  115. 	    vif.wvalid<=1'b1;

  116. 	    if(i=txn.awlen+1) vif.wlast=1;

  117. 	    while (wready=0)

  118.     begin @(posedge vif.clk)

  119.     if (vif.wready==1)

  120. 	    txn.wready=1;

  121.     end

  122.     vif.wlast=0;

  123.     vif.wvalid=0;

  124.     vif.wready=0;

  125.     $display("write data completed");

  126.         end

  127. 	write_ad_incr();

  128.     endtask

  129. 

  130. //////////////////////write_address_incremental/////////////////

  131. virtual task write_ad_incr();

  132.         vif.awlen  <= txn.awlen;

  133. 	for(int i=0; i<(txn.awlen +1);i++)

  134.         vif.awid   <= txn.awid;

  135. 	vif.awaddr <= txn.awaddr;

  136. 	vif.awsize<= txn.awsize;

  137. 	txn.awaddr<= txn.awaddr+(2**awsize);

  138. 	vif.awvalid<= 1;

  139.       wait(vif.awready);

  140. 	vif.awvalid<=0;

  141. 	write_data();

  142. endtask

  143.  virtual task write_data();

  144.      vif.wready<=0;

  145.     for(int i=0;i<=txn.awlen+1;i++) begin

  146. 	    $display("write data started");

  147. 	    vif.wdata<=txn.wdata[i];

  148. 	    vif.wstrb<=txn.wstrb[i];

  149. 	    vif.wid<=txn.wid;

  150. 	    vif.wvalid<=1'b1;

  151. 	    if(i=txn.awlen+1) vif.wlast=1;

  152. 	    while (wready=0)

  153.     begin @(posedge vif.clk)

  154.     if (vif.wready==1)

  155. 	    txn.wready=1;

  156.     end

  157.     vif.wlast=0;

  158.     vif.wvalid=0;

  159.     vif.wready=0;

  160.     $display("write data completed");

  161.     write_ad_wrap();

  162.     end

  163.     endtask

  164. 

  165.     ///////////wri_address_wrap///////////////////////

  166.     virtual task write_ad_wrap();

  167.     vif.awlen  <= '{1,3,7,15};

  168.         vif.awid   <= txn.awid;

  169. 	vif.awaddr <= txn.awaddr;

  170. 	vif.awsize<= txn.awsize;

  171. 

  172.      begin

  173. 	     int burst_length=(awlen+1);

  174. 	     int burst_size=(awsize+1);

  175. 	     int lower_boundary=INT[awaddr/(burst_length*burst_size)]*(burst_length*burst_size);

  176. 	     int upper_boundary=lower_boundar+(burst_length*burst_size);

  177. 	      for (int i=0; i< (pkt.awlen+1);i++)

  178.              begin	     

  179.               if(vif.awaddr==upper_boundary)

  180. 		      vif.awaddr=lower_boundary;

  181. 	      else

  182.       vif.awaddr <= vif.awaddr+ (2**vif.awsize);

  183. 	vif.awvalid<= 1;

  184.       wait(vif.awready);

  185. 	vif.awvalid<=0;

  186. end

  187.       write_data();

  188.       endtask

  189. 

  190.       virtual task write_data();

  191.                     vif.wready<=0;

  192.     for(int i=0;i<=txn.awlen+1;i++) begin

  193. 	    $display("write data started");

  194. 	    vif.wdata<=txn.wdata[i];

  195. 	    vif.wstrb<=txn.wstrb[i];

  196. 	    vif.wid<=txn.wid;

  197. 	    vif.wvalid<=1'b1;

  198. 	    if(i=txn.awlen+1) vif.wlast=1;

  199. 	    while (wready=0)

  200.     begin @(posedge vif.clk)

  201.     if (vif.wready==1)

  202. 	    txn.wready=1;

  203.     end

  204.     vif.wlast=0;

  205.     vif.wvalid=0;

  206.     vif.wready=0;

  207.     $display("write data completed");

  208.     write_response();

  209.     end

  210.     endtask

  211.   virtual task write_response();

  212.   if(vif.wvalid&&vif.wready&&vif.wlast)

  213.       wait(bvalid)

  214.      begin	

  215. 	vif.bid = pkt.bid;

  216. 	vif.bresp = pkt.bresp;

  217.       end	

  218. 	vif.bready <= 1	 ;

  219.      for(i=0;i<=awlen+1;i++)

  220.          begin 	     

  221. 	  if(vif.awid==vif.bid)

  222.                case(vif.bresp)

  223. 		       2'b00:"okay";

  224. 		       2'b01:"exclusive okay";

  225. 		       2'b10:"slave error";

  226. 		       2'b11:"decode error";

  227. 	       endcase

  228.        end

  229. 	       vif.bready<=0;

  230.        endtask

  231. 

  232. 

  233.   ///////////////////////Read address////////////////////////////////////////////////

  234. 

  235. 

  236.        task read_adress();

  237. 

  238. 	`uvm_info("master_driver",$sformatf("message from driver\n %s",pkt.sprint()),UVM_HIGH)

  239. 

  240. 	vif.arid <= pkt.arid;

  241. 	vif.araddr <= pkt.araddr;

  242. 	vif.arlen <= pkt.arlen;

  243. 	vif.arsize <= pkt.arsize;

  244. 	vif.arburst <= pkt.arburst;

  245. 	vif.arvalid <= 1;

  246. 	`uvm_info("master_driver",$sformatf("message from driver \n %s",pkt.sprint()),UVM_HIGH)

  247. 	

  248. 	case (txn.arburst)

  249. 

  250. 		2'b00 : read_address_fixed_burst;

  251. 		2'b01 : read_address_incr_burst;

  252. 		2'b10 : read_address_wrap_burst;

  253. 

  254. 	endcase

  255. 

  256. 	@(posedge vif.clk);

  257. 		

  258. 	wait (vif.arready);

  259. 

  260. 	vif.arvalid <= 0;

  261. 	

  262. endtask

  263. //////////////////////////////////////// raed wrap burst////////////////////

  264.  virtual task read_ad_wrap();

  265.     vif.awlen  <= '{1,3,7,15};

  266.         vif.arid   <= txn.arid;

  267. 	vif.araddr <= txn.araddr;

  268. 	vif.arsize<= txn.arsize;

  269. 

  270.      begin

  271. 	     int burst_length=(arlen+1);

  272. 	     int burst_size=(arsize+1);

  273. 	     int lower_boundary=INT[araddr/(burst_length*burst_size)]*(burst_length*burst_size);

  274. 	     int upper_boundary=lower_boundar+(burst_length*burst_size);

  275. 	      for (int i=0; i< (pkt.arlen+1);i++)

  276.              begin	     

  277.               if(vif.araddr==upper_boundary)

  278. 		      vif.araddr=lower_boundary;

  279. 	      else

  280.       vif.araddr <= vif.araddr+ (2**vif.arsize);

  281. 	vif.arvalid<= 1;

  282.       wait(vif.arready);

  283. 	vif.arvalid<=0;

  284. end

  285.       read_data1();

  286.       endtask

  287. 

  288.   virtual task read_data1();

  289.                     vif.rready<=0;

  290.     for(int i=0;i<=txn.arlen+1;i++) begin

  291. 	    $display("read data started");

  292. 	    vif.rdata<=txn.rdata[i];

  293. 	    vif.rid<=txn.rid;

  294. 	    vif.rvalid<=1'b1;

  295. 	    if(i=txn.arlen+1) vif.rlast=1;

  296. 	    while (rready=0)

  297.     begin @(posedge vif.clk)

  298.     if (vif.rready==1)

  299. 	    txn.rready=1;

  300.     end

  301.     vif.rlast=0;

  302.     vif.rvalid=0;

  303.       $display("read data completed");

  304.     end

  305. 	foreach (vif.rdata[i])

  306. 	begin	

  307. 		if (vif.arid == vif.rid)

  308. 		begin

  309. 			case (vif.rresp)

  310. 

  311. 				2'b00 : s = "Transaction OKAY";

  312. 				2'b01 : s = "Transaction FAILED";

  313. 				2'b10 : s = "SLAVE ERROR";

  314. 				2'b11 : s = "DEEOCDE ERROR";

  315. 			

  316. 			endcase

  317. 				

  318. 		`uvm_info("axi master_driver",$sformatf("\n t %s response for the received data \n",s),UVM_MEDIUM)

  319. 	

  320. 		end

  321. 	end

  322. 	

  323. 	vif.rready <= 0;

  324. 

  325. endtask

  326. 

  327. 

  328. 

  329. 

  330. ////////////////////////////////////////  INCR address    ////////////////

  331. task read_address_incr_burst();

  332. 	vif.arlen <=txn.arlen;

  333. 	for(int i=0; i<(arlen +1);i++)

  334. 	begin

  335. 		vif.araddr<=txn.araddr;

  336.         	vif.arid   <= txn.arid;

  337. 		vif.arvalid<= 1;

  338. 		pkt.araddr<= txn.araddr +(2**vif.arsize);

  339. 		wait(vif.arready);

  340. 		vif.arvalid<=0;

  341. 

  342. 	end

  343. read_data();

  344. endtask

  345. 

  346.  virtual task read_data();

  347.                     vif.rready<=0;

  348.     for(int i=0;i<=txn.arlen+1;i++) begin

  349. 	    $display("read data started");

  350. 	    vif.rdata<=txn.rdata[i];

  351. 	    vif.rid<=txn.rid;

  352. 	    vif.rvalid<=1'b1;

  353. 	    if(i=txn.arlen+1) vif.rlast=1;

  354. 	    while (rready=0)

  355.     begin @(posedge vif.clk)

  356.     if (vif.rready==1)

  357. 	    txn.rready=1;

  358.     end

  359.     vif.rlast=0;

  360.     vif.rvalid=0;

  361.       $display("read data completed");

  362. end	

  363. 	vif.rready <= 1;

  364. 	

  365. 	foreach (vif.rdata[i])

  366. 	begin	

  367. 		if (vif.arid == vif.rid)

  368. 		begin

  369. 			case (vif.rresp)

  370. 

  371. 				2'b00 : s = "Transaction OKAY";

  372. 				2'b01 : s = "Transaction FAILED";

  373. 				2'b10 : s = "SLAVE ERROR";

  374. 				2'b11 : s = "DEEOCDE ERROR";

  375. 			

  376. 			endcase

  377. 				

  378. 		`uvm_info("master_driver",$sformatf("\n\t %s response for the recieved data \n",s),UVM_MEDIUM)

  379. 	

  380. 		end

  381. 	end

  382. 	

  383. 	vif.rready <= 0;

  384. 	

  385. endtask

  386. ///////////////read address fixed burst////////////////////////

  387. task read_address_fixed_burst ();

  388. begin

  389. 	vif.arlen  <= txn.arlen;

  390.         vif.arid   <= txn.arid;

  391. 	vif.araddr <= txn.araddr;

  392. 	vif.arvalid<= 1;

  393. wait(vif.arready);

  394. 	vif.arvalid<=0;

  395. 	end 

  396. 	rd_dt_fixed_burst();

  397. 

  398. endtask

  399. 

  400. 

  401. 

  402. task rd_dt_fixed_burst ();

  403. 	    vif.rready<=0;

  404.     for(int i=0;i<=txn.arlen+1;i++) begin

  405. 	    $display("read data started");

  406. 	    vif.rdata<=txn.rdata[i];

  407. 	    vif.rid<=txn.rid;

  408. 	    vif.rvalid<=1'b1;

  409. 	    if(i=txn.arlen+1) vif.rlast=1;

  410. 	    while (rready=0)

  411.     begin @(posedge vif.clk)

  412.     if (vif.rready==1)

  413. 	    txn.rready=1;

  414.     end

  415.     vif.rlast=0;

  416.     vif.rvalid=0;

  417.       $display("read data completed");

  418. end	

  419. 	foreach (vif.rdata[i])

  420. 	begin	

  421. 		if (vif.arid == vif.rid)

  422. 		begin

  423. 			case (vif.rresp)

  424. 

  425. 				2'b00 : s = "Transaction OKAY";

  426. 				2'b01 : s = "Transaction FAILED";

  427. 				2'b10 : s = "SLAVE ERROR";

  428. 				2'b11 : s = "DEEOCDE ERROR";

  429. 			

  430. 			endcase

  431. 				

  432. 		`uvm_info("master_driver",$sformatf("\n\t %s response for recieved data \n",s),UVM_MEDIUM)

  433. 	

  434. 		end

  435. 	end

  436. 	

  437. 	vif.rready <= 0;

  438. 

  439. endtask

  440.       

  441.       if(txn.resest==1) begin

  442.        reset();

  443.      end     

  444.       //Write operation support

  445.       else if(txn.wr_rd==1) begin  

  446.         `uvm_info(get_type_name()," write packet is received in driver ",UVM_MEDIUM) 

  447. begin

  448. 	write_address();

  449. end

  450.           

  451.     //read operation support

  452.       else if( txn.wr_rd==0) 

  453.       begin    

  454. 	read_address();

  455.       end   

  456.  	seq_item_port.item_done();

  457.  end

  458.  endtask

  459. endclass

  460.