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  1. [Yesterday 10:04 am] Mandla Ravali
  2. class axi_seq_item extends uvm_sequence_item;
  3. //factory registration for object
  4. 'uvm_object_utils(axi_seq_item);
  5. //////write address channel///////////////
  6. bit wr_rd;
  7. bit reset;
  8. randc logic [31:0] awaddr;
  9. rand logic [3:0] awlen;
  10. rand logic [2:0] awsize;
  11. rand logic [1:0] awburst;
  12. rand logic [1:0] awlock;
  13. rand logic [3:0] awcache;
  14. bit awvalid;
  15. bit awready;
  16. bit [1:0] awlock;
  17. rand logic [2:0] awprot;
  18. bit [3:0] awid;
  19. /////////write data channel//////////////
  20. bit [3:0] wid;
  21. bit [2:0] wstrb[];
  22. logic [7:0] wdata[];
  23. bit [1:0] bresp
  24. bit wvalid;
  25. bit wready;
  26. bit wlast;
  27. bit wstrb;
  28. //////read address channel /////////////////
  29. bit [3:0] arid;
  30. randc logic [31:0] araddr;
  31. rand logic [2:0] arsize;
  32. rand logic [1:0] arburst;
  33. rand logic [3:0] arlen;
  34. rand logic [2:0] arprot;
  35. rand logic [1:0] arlock;
  36. rand logic [3:0] arcache;
  37. bit arvalid;
  38. bit arready;
  39. ///////////read data channel////////////
  40. bit [3:0] rid;
  41. logic [7:0] rdata;
  42. bit rresp;
  43. bit rvalid;
  44. bit rready;
  45. bit rlast;
  46. function new (input string name = "axi_seq_item");
  47. super.new(name);
  48. endfunction
  49. ////4kb boundary///////////////////
  50. constraint awaddr_4k{ awaddr % 4096 <= {(awaddr+(awsize*awlen) % 4096;}
  51. constraint araddr_4k{ araddr % 4096 <= {(araddr+(arsize*arlen) % 4096;}
  52. ////last two bits of aligned address should be zero//////////
  53. constraint ali_w_addr{ awaddr[1:0]==0;}
  54. constraint ali_r_addr{ araddr[1:0]==0;}
  55. //constraint burst_type{ awburst==2'b01;arburst==2'b01;}// burst type INCR
  56. //////id's shoud be same for read and write////////////
  57. constraint wr_id{ wid==awid;}
  58. constraint rd_id{ rid==arid;}
  59. constraint rd_rid{rid inside {[wid,awid];}}
  60. //constraint wr_id{ wid inside{[awid]};}
  61. //constraint rd_id{ rid inside{[arid]};}
  62. //////increment burst////////////////////////
  63. constraint wr_data_size{if(awburst==2'b01)
  64. (wdata inside{[1:((2**awsize)*16)]});}
  65. constraint rd_data_size{if(arburst==2'b01)
  66. (rdata inside{[1:((2**arsize)*16)]});}
  67. ///// data for wrap burst///////////////////////////////////
  68. constraint awdata{ if(awburst==2'b10)
  69. wdata inside {((2**awsize)*2),((2**awsize)*4),((2**awsize)*8),((2**awsize)*16)};}
  70. constraint ardata{ if(arburst==2'b10)
  71. wdata inside {((2**arsize)*2),((2**arsize)*4),((2**arsize)*8),((2**arsize)*16)};}
  72. endclass