charan_axi_code

axi_seq.sv

@@ -0,0 +1,61 @@
+ 
+class write_sequence_fixed extends uvm_sequence#(axi_seq_item);
+	 `uvm_object_utils(write_sequence)
+axi_seq_item txn;
+  function new(string name = "write_sequence");
+    super.new(name);
+endfunction
+  virtual task body();
+        `uvm_info(get_type_name(), $sformatf("//---------------- FIXED SEQUENCE is started -----------------//"), UVM_MEDIUM)
+        txn = axi_seq_item::type_id::create("txn");
+        start_item(txn);
+        assert(txn.randomize() with {awburst=2'b00;awlen=3;awsize=4};} );//FIXED
+       	txn.wr_rd=1;
+        finish_item(txn);
+  endtask
+endclass
+class write_sequence_incremental extends uvm_sequence#(axi_seq_item);
+	 `uvm_object_utils(write_sequence)
+axi_seq_item txn;
+  function new(string name = "write_sequence");
+    super.new(name);
+endfunction
+  virtual task body();
+        `uvm_info(get_type_name(), $sformatf("//---------------- INCREMENTAL SEQUENCE is started -----------------//"), UVM_MEDIUM)
+        txn = axi_seq_item::type_id::create("txn");
+        start_item(txn);
+        assert(txn.randomize() with {awburst=2'b10;awaddr==awaddr+2**awsize};} );//INCREMENTAL
+       	txn.wr_rd=1;
+        finish_item(txn);
+  endtask
+endclass
+class write_sequence_wrap extends uvm_sequence#(axi_seq_item);
+	 `uvm_object_utils(write_sequence)
+axi_seq_item txn;
+  function new(string name = "write_sequence");
+    super.new(name);
+endfunction
+  virtual task body();
+        `uvm_info(get_type_name(), $sformatf("//---------------- WRAP SEQUENCE is started -----------------//"), UVM_MEDIUM)
+        txn = axi_seq_item::type_id::create("txn");
+        start_item(txn);
+        assert(txn.randomize() with {awburst=2'b10;awlen=3;awsize=4};} );//WRAP
+       	txn.write=1;
+        finish_item(txn);
+  endtask
+endclass
+class write_sequence extends uvm_sequence#(axi_seq_item);
+	 `uvm_object_utils(write_sequence)
+axi_seq_item txn;
+  function new(string name = "write_sequence");
+    super.new(name);
+endfunction
+  virtual task body();
+        `uvm_info(get_type_name(), $sformatf("//---------------- WRITE SEQUENCE is started -----------------//"), UVM_MEDIUM)
+        txn = axi_seq_item::type_id::create("txn");
+        start_item(txn);
+        assert(txn.randomize() with {foreach(awlen[i]) if(i==awlen+1) wlast==1};} );//for last transfer
+       	txn.wr_rd=1;
+        finish_item(txn);
+  endtask
+endclass

axi_seq_item.sv

@@ -0,0 +1,93 @@
+[Yesterday 10:04 am] Mandla Ravali
+class axi_seq_item extends uvm_sequence_item;
+ 
+//factory registration for object
+
+	'uvm_object_utils(axi_seq_item);
+
+//////write address channel///////////////
+             bit wr_rd;
+             bit reset;
+	randc logic [31:0] awaddr;
+	rand logic [3:0]  awlen;
+	rand logic [2:0]  awsize;
+	rand logic [1:0]  awburst;
+	rand logic [1:0] awlock;
+	rand logic [3:0] awcache;
+	     bit awvalid;
+	     bit awready;
+             bit [1:0] awlock;
+	rand logic [2:0] awprot;
+      	 bit [3:0] awid;
+/////////write data channel//////////////
+             bit [3:0] wid;
+             bit [2:0] wstrb[];
+          logic [7:0] wdata[];
+             bit [1:0] bresp
+	     bit wvalid;
+	     bit wready;
+	     bit wlast;
+	     bit wstrb;
+//////read address channel /////////////////        
+         bit [3:0] arid;
+        randc  logic [31:0] araddr;
+	rand logic [2:0] arsize;
+	rand logic [1:0] arburst;
+	rand logic [3:0] arlen;
+	rand logic [2:0] arprot;
+	rand logic [1:0] arlock;
+	rand logic [3:0] arcache;
+	     bit arvalid;
+	     bit arready;
+ ///////////read data channel////////////
+	 bit [3:0] rid;
+	 logic [7:0] rdata;
+	    bit  rresp;
+	    bit rvalid;
+	    bit rready;
+	    bit rlast;
+function new (input string name = "axi_seq_item");
+	super.new(name);  
+endfunction
+
+////4kb boundary///////////////////
+
+constraint awaddr_4k{ awaddr % 4096 <= {(awaddr+(awsize*awlen) % 4096;} 
+constraint araddr_4k{ araddr % 4096 <= {(araddr+(arsize*arlen) % 4096;}
+
+////last two bits of aligned address should be zero//////////
+
+constraint ali_w_addr{ awaddr[1:0]==0;}
+constraint ali_r_addr{ araddr[1:0]==0;}
+//constraint burst_type{ awburst==2'b01;arburst==2'b01;}// burst type INCR 
+
+//////id's shoud be same for read and write////////////
+constraint wr_id{ wid==awid;}
+constraint rd_id{ rid==arid;}
+constraint rd_rid{rid inside {[wid,awid];}}
+//constraint wr_id{ wid inside{[awid]};}
+//constraint rd_id{ rid inside{[arid]};}
+
+//////increment burst////////////////////////
+constraint wr_data_size{if(awburst==2'b01)
+
+                           (wdata inside{[1:((2**awsize)*16)]});}           
+
+constraint rd_data_size{if(arburst==2'b01)
+
+                           (rdata inside{[1:((2**arsize)*16)]});}
+ 
+ 
+///// data for wrap burst///////////////////////////////////		   
+
+constraint awdata{ if(awburst==2'b10)
+
+                    wdata inside {((2**awsize)*2),((2**awsize)*4),((2**awsize)*8),((2**awsize)*16)};}
+ 
+constraint ardata{ if(arburst==2'b10)
+
+                    wdata inside {((2**arsize)*2),((2**arsize)*4),((2**arsize)*8),((2**arsize)*16)};}
+
+endclass
+ 
+