diff --git a/axi_intrfc.sv b/axi_intrfc.sv
new file mode 100755
index 0000000..3813e0f
--- /dev/null
+++ b/axi_intrfc.sv
@@ -0,0 +1,65 @@
+Interfate axi_intf(input bit clk, reset);
+///////////////////write address channel/////////////
+ input  logic  awvalid; 
+ output logic awready; input  logic  [3:0] awid; 
+ input  logic  [3:0] awlen;
+ input  logic  [2:0] awsize;
+ input  logic  [31:0] awaddr; 
+ input  logic  [1:0] awburst; 
+
+ /////////////////////write data channel//////////////////////////
+ input  logic  wvalid;
+ output logic  wready;
+ input  logic  [3:0] wid;
+ input  logic  [31:0] wdata;
+ input  logic  [3:0] wstrb;
+ input  logic  wlast;
+ ///////////////write response channel/////////////////////
+ input  logic  bready;
+ output logic  bvalid;
+ output logic  [3:0] bid;
+ output logic  [1:0] bresp;
+
+ ////////////// read address channel////////////////
+ output logic  reg arready;
+ input  logic  [3:0] arid; 
+ input  logic  [31:0] araddr; 
+ input  logic  [3:0] arlen; 
+ input  logic  [2:0] arsize;
+ input  logic  [1:0] arburst;
+ input  logic  arvalid;
+
+///////////////////read data channel////////////////////
+output logic  [3:0] rid; 
+output logic  [31:0]rdata; 
+output logic  [1:0] rresp;
+output logic   rlast; 
+output logic   rvalid; 
+input  logic   rready;
+
+
+
+////////////////////bvalid assertion//////////////
+property wvalid_wready;
+	@(posedge clk) (wvalid && wready)|=> bvalid;
+endproperty
+
+assert property(wvalid_wready)
+$display("bvalid is asserted after wvalid and wready:assertion passed");
+ else
+'uvm_error("assertion failed");
+
+////////////////////rvalid assertion//////////////
+
+property arvalid_arready;
+	@(posedge clk) (arvalid && arready)|=> rvalid;
+endproperty
+
+assert property(arvalid_arready)
+$display("rvalid is asserted after arvalid and arready:assertion passed");
+ else
+'uvm_error("assertion failed");
+
+endinterface
+
+